Internal clock signals for a memory device are typically derived from a core system clock. The core system clock signal generally has a lower frequency than is desirable for internal clock signals, and consequently, higher frequency clock signals are generated from the core system signal for use as internal clock signals. The higher frequency clock signals generally have a frequency that is a multiple of the frequency of the core clock signal. For example, it is not unusual for internal clock signals to have a clock frequency that is two, three, or four times the core clock signal frequency. Techniques for generating clock signals having higher frequencies from the core clock signal are well known. Generally, it can be described that the core system clock is in a first clock domain and the internal clock signals having a common higher clock frequency are in a second clock domain, and similarly, internal clock signals having the same, but even higher clock frequency, are yet in a third clock domain. In some instances, different devices are operating in different clock domains, but operation needs to be synchronized. For example, a memory device may be operating in a higher frequency clock domain, but a memory controller communicating with the memory device may be operating in a lower frequency clock domain. However, successful operation of the memory device and memory controller depend on the signals transmitted between the two meeting established timing relationships.
Typically, the higher frequency clock signals that are generated from the core clock signal have a fixed phase relationship with the core clock signal. For example, as shown in FIG. 1, an internal clock signal 108 having twice the clock frequency of a core clock signal 104 has rising edges that are coincident, or synchronized, with each clock edge of the core clock signal. Thus, at time T0 and T1, clock transitions of the core clock signal and the internal clock signal 108 are coincident. Similarly, an internal clock signal 112 having four times the clock frequency of the core clock signal 104 has a different, but also fixed, phase relationship with the core clock signal. More specifically, the rising edge of every other clock pulse of the internal clock signal 112 is synchronized with every clock transition of the core clock signal 104. As shown in FIG. 1, the core clock signal 104 and the internal clock signal 112 have clock transitions that are coincident at the times T0 and T1.
It is often desirable to adjust the phase relationship of an internal clock signal with respect to the core clock signal from which internal clock signal is generated. Adjusting the phase relationship provides the ability to accommodate inherent time delays that alter the expected phase relationship. For example, phase shifts can result from line loading issues, varying line impedances, and propagation delays. Another example is different lengths of different conductive signal paths will cause different time delays. Thus, two synchronized clock signals on two different length signal paths will have two different time delays, and consequently, arrive at their respective destinations at different times. Where an operation relies on the synchronization of the two clock signals, clearly this situation is undesirable.
Additionally, delay circuits can also be used to alter the relative timing of signals to modify various timing margins of signals. That is, signals that are internal to a memory device, as well as signals that are provided externally of the memory device, can have the timing adjusted with respect to the timing of other signals in order to provide greater or lesser timing margins, but still remain within published timing specifications. For example, where a memory controller is coupled to a memory device, and a write operation is to be requested, the relative timing of a write data strobe with respect to the transmission of data can be modified through the use of delay circuits in order to shift the time relationship at which the write data strobe is provided to the memory device by the memory controller and when the data is actually provided by the memory controller to the memory device. Having the flexibility to change the relative timing of internal and external signals, including external signals that are provided between different devices, is often desirable in order to accommodate process and device variations that result in performance variations.
The relative phase of a clock signal can be adjusted by adding a delay into the signal path of the clock signal. The added time delay to a clock signal causes the clock signal to shift in time, thus, resulting in the phase of the delayed clock signal shifting. A time delay can be selected such that a clock signal that would otherwise become unsynchronized because of the inherent time delays is further delayed so that the clock signal can again be synchronized. An adjustable delay circuit provides the flexibility of adjusting the time delay added to the clock signal. With many conventional delay circuits, the time delay is adjusted by changing a value applied to the delay circuit that is indicative of the amount of time delay desired. Such adjustable delay line circuits are well known in the art.
A problem related to conventional delay circuits is that glitch or runt pulses are often output from the delay circuit in response to changing the time delay. In some cases, the particular design of the delay circuit is inherently susceptible to generating glitch pulses when the time delay is changed. Factors such as the timing of an input clock signal relative to when a delay circuit is disabled in order to change the time delay or switching noise also contribute to the generation of glitch pulses. The problem results from the possibility that the glitch pulses may inadvertently trigger a response by a circuit coupled to the output of the delay circuit. Thus, when changing the time delay of a delay circuit, an errant pulse may cause unexpected results.
Another problem with using conventional delay lines arises with respect to maintaining a phase relationship between a first clock signal and a second, higher frequency clock signal, when adjusting the time delay of a delay line circuit used in delaying the second clock signal. In the process of adjusting the time delay of the delay circuit, the phase relationship of the second clock signal relative to the first clock signal may be lost. More specifically, a circuit that performs a function in response to the second clock signal, that results in performing the function generally coincident with a clock transition of the first clock signal, can end up performing the function at the wrong time with respect to the first clock signal because the phase relationship of the second clock signal changes relative to the first clock signal is lost when the time delay is adjusted.
For example, FIG. 2 shows a first clock signal 202 and a second clock signal 204 that is generated based on the first clock signal 202. The second clock signal 204 has a frequency that is twice that of the first clock signal 202, and is in phase with the first clock signal 202. A third clock signal 206 also shown in FIG. 2 is a delayed version of the second clock signal 204 having a time delay Td1 relative to the second clock signal 204. The time delay of the third clock signal 206 is provided by an adjustable delay line circuit (not shown). The third clock signal 206 is used for timing a circuit, for example, timing a conventional latch circuit (not shown) that outputs data in response to every other rising edge of the third clock signal 206. The rising edge of the third clock signal 206 that causes data to be output is generally coincident with the rising edge of the first clock signal 202. As a result, data 220 is output in response to the rising edge of the third clock signal 206 at a time T1, which generally coincides with the rising edge of the first clock signal 202 at a time T0. Similarly, data 222 is output in response to the rising edge of the third clock signal 206 at a time T3, which generally coincides with the rising edge of the first clock signal 202 at a time T2.
FIG. 2 further illustrates a clock signal 206′ having a new time delay Td2 relative to the second clock signal 204. The clock signal 206′ represents the second clock signal after the time delay of the adjustable delay circuit is changed to the new time delay Td2. As previously described, the latch circuit receiving the clock signal 206′ outputs data in response to every other rising edge. Thus, data 224 is output in response to the rising edge of the clock signal 206′ at a time T5, and data 226 is output in response to the rising edge of the clock signal 206′ at a time T7. However, as shown in FIG. 2, in changing the time delay of the delay line circuit, the phase relationship between the third clock signal 206 and the first clock signal 202 is lost. The first rising edge of the clock signal 206′ at a time T5 is in response to the rising edge of the second clock signal 204 at a time T4. Consequently, the time at which data is output by the latch is no longer generally coincident with the rising edge of the first clock signal 202. As shown in FIG. 2, the data 224 and 226 are output generally coincident with the falling edges of the first clock signal 202 at times T4 and T6, respectively. The clock signals 206 and 206′ illustrate how changing the time delay of a conventional delay circuit may result in an output clock signal losing its phase relationship relative to another clock signal. With respect to FIG. 2, the lost phase relationship results in data being output by the latch circuit 180 degrees out of phase from when it should be output. Additionally, where other circuitry in the memory device or a memory controller coupled to the memory device are synchronized by respective clock signals that are also based on the second clock signal 204, the latch circuit of the present example is now no longer synchronized with the other circuitry either within the memory device or with the memory controller, and consequently, an error will undoubtedly occur Clearly, the situation described with respect to FIG. 2 would be undesirable.